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| 4.2 5 gbps , 16 16, digital crosspoint switch data sheet ADN4604 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringemen ts of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered t rademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2009C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features dc to 4.25 gbps per port nrz data rate programmable receive equalization 12 db boost at 2 ghz compensates 40 inches of fr4 at 4.25 gbps programmable transmit preemphasis/deemphasis up to 12 db boos t at 4.25 gbps compensates 40 inches of fr4 at 4.2 5 gbps low power : 1 3 0 mw per channel at 3.3 v (outputs enabled) 16 16, fully differential, non blocking array double rank connection programming with dual connection maps low jitter, typically 20 ps flexible i/o supply range dc - or ac - coupled differential cml inputs programmable cml output levels per - l ane input p/n pair inversion for routing ease 50 on - chip i/o termination supports 8b / 10b, scrambled or uncoded nrz data serial ( i 2 c slave or spi ) control interface 100- lead tqfp , pb - free package applicatio ns fiber optic network switching high speed serial backplane routing to oc - 48 with fec xaui : 10gbase - kx4 gigabit ethernet over backplane: 1000base - kx 1 , 2 , and 4 fibre chann el infini b and ? digital video (hdmi, dvi, displayport, 3g - /hd - /sd - sdi) data stora ge networks functional block dia gram eq rx tx pre- emphasis 16 16 switch m a trix connection ma p 0 connection ma p 1 seria l inter f ace contro l logic per-port output leve l settings output leve l hooku p t able ADN4604 v cc v ee dv cc op[15:0] v tton , v ttos on[15:0] ip[15:0] v ttie , v ttiw in[15:0] i2c/spi addr1/sdi sda/sdo scl/sck reset update addr0/cs 07934-001 figure 1 . general description the ad n4604 is a 16 16 asynchronous, protocol agnostic, digital crosspoint switch, with 16 differential pecl - /cml - compatible inputs and 16 differential cm l outputs. the ad n4604 is optimized for nonreturn - to - zero ( nrz ) sig - na ling with data rates of up to 4.25 gbps per port. each port offers a fixed level of input equalization and programmable output swing and output preemphasis . the ADN4604 non blocking swi tch core implements a 16 16 crossbar and supports independent channel switching through the serial control interface. the ADN4604 has low latency and very low channel - to - channel skew. an i 2 c? or spi interface is used to control the device and pro - vide ac cess to advanced features, such as additional levels of preemphasis and output disable. the ADN4604 is packaged in a 100- lead tqfp package and operate s from ? 40 c to +85 c.
ADN4604 data sheet rev. a | page 2 of 40 table of contents fe atures .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general descr iption ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical specific ations ............................................................... 3 i 2 c timing specifications ............................................................ 4 spi timing specifications ........................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 16 introduction ................................................................................ 16 receivers ...................................................................................... 16 switch core ................................................................................. 17 transmitters ................................................................................ 19 termination ................................................................................. 23 i 2 c serial control interface ........................................................... 24 reset ............................................................................................. 24 i 2 c dat a wr ite ............................................................................. 24 i 2 c data read .............................................................................. 25 spi serial control interface .......................................................... 26 register map ................................................................................... 28 applications information .............................................................. 32 supply sequencing ..................................................................... 34 power dissipation ....................................................................... 34 output compliance ................................................................... 34 printed circuit board (pcb) layout guidelines ................... 36 outline dimensions ....................................................................... 38 ordering guide .......................................................................... 38 revision history 3/13 rev. 0 to rev. a changes to switching time parameter a nd operating range parameter, table 1 .......................................................................................... 3 changes to logic characteristics parameters, table 1 ................... 4 changes to receivers section ...................................................................... 16 changes to switch core section ................................................................. 17 changes to transmitters section and figure 42 ...................................... 19 changes to basic settings section and table 1 1 ....................................... 20 change to table 18 ....................................................................................... 29 10 /09 revision 0: initial version data sheet ADN4604 rev. a | page 3 of 40 specifications electrical specifica tions v cc = 3.3 v, v tti x = 3.3 v, v tto x = 3.3 v, dv cc = 3.3 v, v ee = 0 v, r l = 50 ? , data rate = 4.25 gbps, ac - coupled inputs and outputs, differential i nput s wing = 800 mv p - p , t a = 27 c, unless otherwise noted. table 1. parameter conditions min typ max unit dynamic performance data rate (dr) per channel (nrz) dc 4.25 gbps deterministic jitter data rate = 4.25 gbps, no channel 20 ps p - p random jitter rms, no channel 1 ps rms residual deterministic jitter with receive equalization data rate = 4.25 gbps, 20 in. fr4, eq boost = 12 db 27 ps p - p data rate = 4.25 gbps, 30 in. fr4, eq boost = 12 db 43 ps p - p data rate = 4.25 gbps, 40 in. fr4, eq boost = 12 db 70 ps p - p residual deterministic jitter with transmit preemphasis data rate = 4.25 gbps, 20 in . fr4, pe boost = 4.2 db 23 ps p - p data rate = 4.25 gbps, 30 in . fr4, pe boost = 6 db 25 ps p - p data rate = 4.2 5 gbps, 40 in . fr4, pe boost = 6 db 35 ps p - p propagation delay input to output , eq boost = 12 db 800 ps channel - to - channel skew 50 ps switching time measured from v il level of falling edge of update to 50% of output signal transition 100 ns output rise/fall time 20% to 80% 75 ps input characteristics differential input voltage swing v icm 1 = v cc ? 0.6 v; v cc = v min to v max , t a = t min to t max 200 2000 mv p - p diff input voltage range single - ended absolute voltage level, v l v ee + 1.1 v single - ended absolute voltage level, v h v cc + 0.3 v output characteristics output voltage swing differential, pe boost = 0 db, default output level, at dc 600 800 900 mv p - p diff output voltage range single - ended absolute voltage level, v l v cc C 1.3 v single - ended absolute voltage level, v h v cc + 0.2 v per - port output current pe boost = 0 db, default output level 16 ma pe boost = 6 db, default output level 32 ma termination characteristics resistance single - ended , v cc = 2. 7 v to 3.6 v , v tti = 2.2 v to 3.6 v, v tto = 2.2 v to 3.6 v , t a = t min to t max ; 44 50 56 ? temperature coefficient 0.025 ? / c power supply operating range v cc v ee = 0 v 2.7 3.3 3.6 v dv cc v ee = 0 v 2.7 3.3 3.6 v v ttie , v ttiw v ee = 0 v , v cc = 3.3 v 1.3 3.3 v cc + 0.3 v v tton , v ttos v ee = 0 v , v cc = 3.3 v 2.2 2 3.3 v cc + 0.3 v supply current outputs disabled i cc 95 110 ma i dv cc 20 35 ma i tti e + i tti w + i tto n + i tt os 0 10 ma supply current all outputs enabled, ac - coupled i/o, 4 00 mv i/o swings (800 mv p - p differential), pe boost = 0 db, 50 ? far- end terminations i cc 342 370 ma i dvcc 20 3 5 ma i ttie + i ttiw + i tton + i ttos 256 2 80 ma supply current all outputs enabled, ac - coupled i/o, 400 mv i/o swings (800 mv p - p differential), pe boost = 6 db, 50 ? far- end terminations i cc 486 540 ma i dvcc 20 3 5 ma i ttie + i ttiw + i tton + i ttos 512 540 ma ADN4604 data sheet rev. a | page 4 of 40 parameter conditions min typ max unit thermal characteristics operating temperature range ?40 +85 c ja still air; jedec 4-layer test board 24.9 c/w jb still air 11.6 c/w jc at the exposed pad 0.95 c/w logic characteristics input high voltage threshold (v ih ) dv cc = 3.3 v 0.7 dv cc dv cc v input low voltage threshold (v il ) dv cc = 3.3 v v ee 0.3 dv cc v output high voltage (v oh ) 2 k pull-up resistor to dv cc dv cc v output low voltage (v ol ) i ol = 3 ma v ee 0.4 v 1 v icm is the input common-mode voltage. 2 minimum v tto is only applicable for a limited range of output current settings. refer to the power dis sipation section. i 2 c timing specifications 07934-002 s p sr s sda scl t f t f t f t f t buf t low t hd:sta t hd:dat t high t su:dat t su:sta t su:sto t hd:sta figure 2. i 2 c timing diagram table 2. i 2 c timing specifications parameter symbol min max unit scl clock frequency f scl 0 400+ khz hold time for a start condition t hd;sta 0.6 s setup time for a repeated start condition t su;sta 0.6 s low period of the scl clock t low 1.3 s high period of the scl clock t high 0.6 s data hold time t hd;dat 0 s data setup time t su;dat 10 ns rise time for both sda and scl t r 1 300 ns fall time for both sda and scl t f 1 300 ns setup time for stop condition t su;sto 0.6 s bus-free time between a stop condition and a start condition t buf 1 ns bus idle time after a reset 10 ns reset pulse width 10 ns data sheet ADN4604 rev. a | page 5 of 40 spi timing specifications t 1 t 2 t 3 t 5 t 6 t 4 t 8 t 7 a7 cs sck sdi sdo a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxxxxxxxxx x 07934-003 figure 3. spi write timing diagram t 1 t 2 t 9 t 3 t 5 t 6 t 4 t 7 t 8 a7 cs sck sdi a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 x sdo x x x x x x x d7d6d5d4d3d2d1 d0 07934-004 figure 4. spi read timing diagram table 3. spi timing specifications parameter symbol min max unit sck clock frequency f sck 0 10 mhz cs to sclk setup time t 1 10 ns sclk high pulse width t 2 40 ns sclk low pulse width t 3 40 ns data access time after sclk falling edge t 4 35 ns data setup time prior to sclk rising edge t 5 20 ns data hold time after sclk rising edge t 6 10 ns cs to sclk hold time t 7 10 ns cs to sdo high impedance t 8 40 ns cs high pulse width t 9 10 ns ADN4604 data sheet rev. a | page 6 of 40 absolute maximum rat ings table 4. parameter rating v cc to v ee 3.7 v dv cc to v ee 3.7 v v tti e , v tti w v cc + 0.6 v v tto n , v tto s v cc + 0.6 v internal power dissipation 1 4.9 w differential input voltage 2.0 v logic input voltage v ee C 0.3 v < v in < v cc + 0.6 v storage te mperature range ? 65 c to +125 c lead temperature range 30 0c junction temperature 1 50 c 1 internal power dissipation is for the device in free air. t a = 27c; ja = 24.9c/w in still air. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution data sheet ADN4604 rev. a | page 7 of 40 pin configuration an d function descriptions pin 1 ADN4604 t op view (not to scale) 1 reset 2 ip0 3 in0 4 v cc 5 ip1 6 in1 7 v ttiw 8 ip2 9 in2 10 v ee 1 1 ip3 12 in3 13 v cc 14 ip4 15 in4 16 v ee 17 ip5 18 in5 19 v ttiw 20 ip6 21 in6 22 v cc 23 ip7 24 in7 25 upd a te 2 6 i2c/spi 2 7 op0 2 8 on0 2 9 v ee 3 0 op1 3 1 on1 3 2 v tt os 3 3 op2 3 4 on2 3 5 v cc 3 6 op3 on3 37 3 8 v ee 3 9 op4 4 0 on4 4 1 v cc 4 2 op5 4 3 on5 4 4 v tt os 4 5 op6 4 6 on6 47 v ee 4 8 op7 4 9 on7 5 0 addr1/sdi 7 6 scl/sck 7 7 op8 7 8 on8 7 9 v ee 8 0 op9 8 1 on9 8 2 v tt on 8 3 op10 8 4 on10 8 5 v cc 8 6 op 1 1 8 7 on 1 1 8 8 v ee 8 9 op12 9 0 on12 9 1 v cc 9 2 op13 9 3 on13 9 4 v tt on 9 5 op14 9 6 on14 9 7 v ee 9 8 op15 9 9 on15 1 0 0 dv cc 5 1 addr0/cs 5 2 ip8 5 3 in8 5 4 v cc 5 5 ip9 5 6 in9 5 7 v ttie 5 8 ip10 5 9 in10 6 0 v ee 6 1 ip 1 1 6 2 in 1 1 6 3 v cc 6 4 ip12 6 5 in12 6 6 v ee 6 7 ip13 6 8 in13 6 9 v ttie 7 0 ip14 7 1 in14 7 2 v cc 7 3 ip15 7 4 in15 7 5 sda/sdo 07934-005 notes 1. the ADN4604 tqfp has an exposed paddle (epad) on the underside of the package that aids in heat dissipation. the epad must be electrically connected to the v ee supply plane to meet thermal specifications. 2. sda/scl/addr1/0 for i 2 c operation. sck/sdo/sdi/cs for spi operation. figure 5 . pin configuration ADN4604 data sheet rev. a | page 8 of 40 table 5 . pin function descriptions pin no. mnemonic type description 1 reset control configuration registers reset, active low . this pin is n ormally pulled up to dv cc . 2 ip0 input high speed input . 3 in0 input high speed input complement . 4, 13, 22, 35, 41, 54, 63, 72, 85, 91 v cc power positive supply . 5 ip1 input high speed input . 6 in1 input high speed input complement . 7, 19 v ttiw po wer input termination supply (west) . these pins are normally tied to the v ttie pins . 8 ip2 input high speed input . 9 in2 input high speed input complement . 10, 16, 29, 38, 47, 60, 66, 79, 88, 97, e pad v ee power negative supply . 11 ip3 input high spee d input . 12 in3 input high speed input complement . 14 ip4 input high speed input . 15 in4 input high speed input complement . 17 ip5 input high speed input . 18 in5 input high speed input complement . 20 ip6 input high speed input . 21 in6 input high spe ed input complement . 23 ip7 input high speed input . 24 in7 input high speed input complement . 25 update control second rank write enable, active low. this pin is normally pulled up to d v cc . 26 i2c /spi control i 2 c/ spi control interface selection, i 2 c active low . 27 op0 output high speed output . 28 on0 output high speed output complement . 30 op1 output high speed output . 31 on1 output high speed output complement . 32, 44 v ttos power output termination supply (so uth) . these pins are n ormally tied to the v tton pins . 33 op2 output high speed output . 34 on2 output high speed output complement . 36 op3 output high speed output . 37 on3 output high speed output complement . 39 op4 output high speed output . 40 on4 ou tput high speed output complement . 42 op5 output high speed output . 43 on5 output high speed output complement . 45 op6 output high speed output . 46 on6 output high speed output complement . 48 op7 output high speed output . 49 on7 output high speed out put complement . 50 addr1/sdi control i 2 c slave address bit 1 (msb) or spi data input. 51 addr0/ cs control i 2 c slave address bit 0 (lsb) or spi chip select (active low) . 52 ip8 input high speed input . 53 in8 input high speed input co mplement . 55 ip9 input high speed input . 56 in9 input high speed input complement . data sheet ADN4604 rev. a | page 9 of 40 pin no. mnemonic type description 57, 69 v ttie power input termination supply (east) . these pins are normally tied to the v ttiw pins . 58 ip10 input high speed input . 59 in10 input high speed input compl ement . 61 ip11 input high speed input . 62 in11 input high speed input complement . 64 ip12 input high speed input . 65 in12 input high speed input complement . 67 ip13 input high speed input . 68 in13 input high speed input complement . 70 ip14 input hig h speed input . 71 in14 input high speed input complement . 73 ip15 input high speed input . 74 in15 input high speed input complement . 75 sda/sdo control i 2 c data or spi data output . 76 scl/sck control i 2 c clock or spi clock . 77 op8 output high speed o utput . 78 on8 output high speed output complement . 80 op9 output high speed output . 81 on9 output high speed output complement . 82, 94 v tton power output termination supply (north) . these pins are normally tied to the v ttos pins . 83 op10 output high speed output . 84 on10 output high speed output complement . 86 op11 output high speed output . 87 on11 output high speed output complement . 89 op12 output high speed output . 90 on12 output high speed output complement . 92 op13 output high speed output . 93 on13 output high speed output complement . 95 op14 output high speed output . 96 on14 output high speed output complement . 98 op15 output high speed output . 99 on15 output high speed output complement . 100 d v cc power digital positive supply . ADN4604 data sheet rev. a | page 10 of 40 typical performance characteristics v cc = 3.3 v, v ttix = 3.3 v, v ttox = 3.3 v, dv cc = 3.3 v, v ee = 0 v, r l = 50 , data rate = 4.25 gbps, ac-coupled inputs and outputs, differential input swing = 800 mv p-p, t a = 27c, unless otherwise noted. 50 ? cables 2 2 high speed sampling oscilloscope 50 ? cables 2 2 50? ADN4604 ac-coupled evaluation board input pin output pin pattern generator data out tp2 tp1 07934-006 0.167iu/div 200mv/di v reference eye diagram at tp1 figure 6. standard test circuit 200mv/di v 0.167iu/div 07934-007 figure 7. 3.25 gbps input eye (tp1 from figure 6) 200mv/di v 0.167iu/div 07934-008 figure 8. 4.25 gbps input eye (tp1 from figure 6) 200mv/di v 0.167iu/div 07934-009 figure 9. 3.25 gbps output eye (tp2 from figure 6) 200mv/di v 0.167iu/div 07934-010 figure 10. 4.25 gbps output eye (tp2 from figure 6) data sheet ADN4604 rev. a | page 11 of 40 50? cables 2 2 tp3 high speed sampling oscilloscope 50? cables 2 2 50? ADN4604 ac-coupled evaluation board input pin output pin pattern generator data out tp1 50? cables 2 2 tp2 fr4 test backplane differential stripline traces 8mils wide, 8mils space, 8mils dielectric height lengths = 10 inches, 20 inches, 30 inches, 40 inches 0.167iu/div 200mv/div reference eye diagram at tp1 07934-011 figure 11 . equa lization test circuit 200mv/div 0.167iu/div 07934-012 figure 12 . 4.25 gbps input eye, 20 i nch fr4 input channel (tp 2 from figure 11 ) 200mv/div 0.167iu/div 07934-013 figure 13 . 4.25 gbps input eye, 40 - i nch fr4 input chan nel (tp 2 from figure 11) 200mv/div 0.167iu/div 07934-014 figure 14 . 4.25 gbps output eye, 20 - i nch fr4 input channel , eq = 12 db (tp3 from figure 11) 200mv/div 0.167iu/div 07934-015 figure 15 . 4 .25 gbps output eye, 4 0 - i nch fr4 input channel , eq = 12 db (tp3 from figure 11) ADN4604 data sheet rev. a | page 12 of 40 50? cables 2 2 tp3 high speed sampling oscilloscope 50? cables 2 2 50? ADN4604 ac-coupled evaluation board input pin output pin pattern generator data out tp1 50? cables 2 2 tp2 fr4 test backplane differential stripline traces 8mils wide, 8mils space, 8mils dielectric height lengths = 10 inches, 20 inches, 30 inches, 40 inches 07934-016 0.167iu/div 200mv/div reference eye diagram at tp1 figure 16 . preemphasis test circuit 200mv/div 0.167iu/div 07934-017 figure 17 . 4.25 gbps output eye, 20 - i nch fr4 output cha nnel, pe = 0 db (tp3 from figure 16) 200mv/div 0.167iu/div 07934-018 figure 18 . 4.25 gbps output eye, 4 0 - i nch fr4 input channel , pe = 0 db (tp3 from figure 16) 200mv/div 0.167iu/div 07934-019 figure 19 . 4.25 gbps output eye, 2 0 - i nch fr4 input channe l , pe = 4.2 db (tp3 from figure 16) 200mv/div 0.167iu/div 07934-020 figure 20 . 4.25 gbps output eye, 4 0 - i nch fr4 input channel , pe = 6 db (tp3 from figure 16) data sheet ADN4604 rev. a | page 13 of 40 0 20 40 60 80 100 0 1 2 3 4 5 deterministic jitter (ps) d at a r a te (gbps) 07934-036 eq = 12db eq = 0db f igure 21 . deterministic jitter vs. data rate 0 20 40 60 80 100 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.6 3.5 deterministic jitter (ps) supp l y vo lt age (v) eq = 12db eq = 0db 07934-034 figure 22 . deterministic jitter vs. supply voltage 0 20 40 60 80 100 ?40 ?20 0 20 40 60 80 deterministic jitter (ps) temper a ture (c) 07934-035 eq = 0db eq = 12db figure 23 . deterministic jitter vs. temperature 0 100 200 300 400 500 600 700 800 900 1000 0 1 2 3 4 5 eye height (mv p-p diff) dat a r a te (gbps) 07934-029 figure 24 . eye height vs. data rate 0 100 200 300 400 500 600 700 800 900 1000 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 eye height (mv p-p diff) supp l y vo lt age (v) 07934-028 figure 25 . eye height vs. supply voltage 0 100 200 300 400 500 600 700 800 900 1000 ?40 ?15 10 35 60 85 eye height (mv p-p diff) temper a ture (c) 07934-037 figure 26 . eye height vs. temperature ADN4604 data sheet rev. a | page 14 of 40 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 deterministic jitter (ps) input fr4 trace length (inches) 07934-031 eq = 12db eq = 0db figure 27 . deterministic jitter vs. input fr4 channel length 0 20 40 60 80 100 0 0.5 1.0 1.5 2.0 deterministic jitter (ps) differentia l input swing (v p-p) 07934-033 eq = 12db eq = 0db figure 28 . deterministic jitter vs. differential input swing 0 10 20 30 40 50 60 70 80 90 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 deterministic jitter (ps) output termin a tion vo lt age v ttox (v) 07934-025 output level = 1200mv p-p diff output level = 800mv p-p diff output level = 200mv p-p diff figure 29 . deterministic jitter vs. output termination voltage (v tto ) 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 deterministic jitter (ps) output fr4 trace length (inches) 0db 2db 4.2db 6db 9.5db 12db 07934-030 7.8db figure 30 . deterministic jitt er vs. output fr4 channel length 0 20 40 60 80 100 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 deterministic jitter (ps) input common-mode vo lt age (v) 07934-032 eq = 0db eq = 12db figure 31 . deterministic jitter vs. input common - mode voltage 07934-038 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 ?16 ?18 1g 100m 10m 1m 100k ?20 loss (db) frequency (hz) 6" 10" 20" 30" 40" figure 32 . s21 test traces data sheet ADN4604 rev. a | page 15 of 40 0 10 20 30 40 50 60 70 80 90 100 ?40 ?20 0 20 40 60 80 rise/ f al l time (ps) temper a ture (c) 07934-026 fall time rise time figure 33 . rise/fall time vs. temperature 500 550 600 650 700 750 800 850 900 950 1000 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 del a y (ps) supp l y vo lt age (v) eq = 0 eq = 12db 07934-023 f igure 34 . pro pagation delay vs. supply voltage 0 5 10 15 20 25 750 760 770 780 790 800 810 820 830 840 hits pro p ag a tion del a y (ps) 07934-021 figure 35 . propagation delay histogram 0 50,000 100,000 150,000 200,000 250,000 300,000 350,000 400,000 450,000 500,000 ?7 ?6 ?5 ?4 ?2 ?3 ?1 0 1 2 3 4 5 6 samples jitter (ps) 07934-024 figure 36 . random jitter histogram 500 550 600 650 700 750 800 850 900 950 1000 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 del a y (ps) temper a ture ( c) eq = 0db eq = 12db 07934-022 figure 37 . propagation delay vs. temperature ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10m 100m 1g 10g return loss (db) frequenc y (hz) s11 s22 xaui_spec 07934-027 figure 38 . return loss (s11, s22) ADN4604 data sheet rev. a | page 16 of 40 theory of operation introduction the ADN4604 is a 16 16, buffered, asynchronous crosspoint switch that provides input equalization, output preemphasis , and output l evel programming capabilities . the receivers integrate an equalizer that is optimized to compensate for typical backplane losses. the switch supports multicast and broadcast operation, allowing the ADN4604 to work in redundancy and port - replication applica tions. the part offers extensively programmable output levels and preemphasis settings. eq rx tx pre- emphasis 16 16 switch m a trix connection ma p 0 connection ma p 1 seria l inter f ace contro l logic per-port output leve l settings output leve l hooku p t able ADN4604 v cc v ee dv cc op[15:0] v tton , v ttos on[15:0] ip[15:0] v ttie , v ttiw in[15:0] i2c/spi addr1/sdi sda/sdo scl/sck reset update addr0/cs 07934-039 figure 39 . block diagram the configuration of the crosspoint is controlled through a serial interface. this interface supports both i 2 c and spi protocols, which can be selected using the i2c /spi dedicated control pin . there are two i 2 c address pins available as described in table 6 . table 6 . serial interface control modes pi n no. i2c /spi = 0 i2c /spi = 1 pin name pin function pin name pin function 50 addr1 i 2 c address msb sdi spi data input 51 addr0 i 2 c address lsb cs spi chip select 75 sda i 2 c data sdo spi dat a output 76 scl i 2 c clock sck spi clock receivers the ADN4604 receiv er inputs incorporate 50 termination resistors, esd protection, and an equalizer that is optimized for operation over long backplane traces. each receive channel also provides a positive/negative (p/n) inversion function, which allows the user to swap th e sign of the input signal path to eliminate the need for board - level crossovers in the receiver channel. v cc v ttix ipx inx v ee simplified receiver input circuit rln rl rlp rl q1 q2 i1 r3 1k? r1 750? r2 750? rn 52? rp 52? 07934-040 figure 40 . simplified input circuit equalization the ADN4604 receiver incorporates a continuous time equali zer (eq) that pr ovides 12 db of high frequency boost to compensate up to 40 inches of fr4 at 4.25 gbps. each input has a n equalizer control bit. by default, the programmable boost is set to 12 db. the boost can be set to 0 db by programming a logic 0 to the respective re gister bit for the corresponding channel. table 7 . equalization control registers eq[15:0 ] equalization boost 0 0 db 1 12 db (default) lane inversion the receiver p/n inversion is a feature intended to allow the user to impleme nt the eq uivalent of a board - level cross over in a much smaller area and without additional via impedance discon tinuities that degrade the high frequency integrity of the signal path. the p/n inversion is available independently for each of the 16 input ch annels and is controlled by writing to the sign bi t of the rx control registers (a ddresses 0x12 and address 0x13). note that using this feature to account for signal inversions downstream of the receiver requires additional attention when switching connect ivity. table 8 . signal path polarity control s ign [15:0 ] signal path polarity 0 non inverting (default) 1 inverting data sheet ADN4604 rev. a | page 17 of 40 switch core the ADN4604 switch core is a fully non blocking 16 16 array that all ows multi cast and broadcast con figurations. the config - uration of the switch core is programmed through the serial control interface. the crosspoint configuration map controls the connectivity of the switch core. the crosspoint configuration map consists of a double - rank register archit ecture where each rank consists of an 8 - byte configuration map as shown in figure 41. the second rank registers contain the cu rrent state of the crosspoint . the first rank registers contain the next s tate. each entry in the connec tion map stores four bits per output, which i ndicates which of the 16 inputs ar e connected to a given output. an entire connectivity matrix can be programmed at once by passing data from the first rank registers into the second rank registers . the first ra nk registers are two separate volatile 8 - byte memory banks which store connection configurations for the cross - point . map 0 is the default map and is located at address 0x90 to address 0x97. by default, m ap 0 contains a diagonal connection configura tion wh ereby i nput 15 is connected to o utput 0, i nput 14 to o utput 1, i nput 13 to o utput 2, and so on. similarly , by default, m ap 1 contains the opposite diagonal connection configuration where i nput 0 is connected to output 0, i nput 1 to o utput 1, and so on. bot h maps are re ad/write accessible registers. the active map is selected by writing to the xpt table select register (a ddress 0x81). the crosspoint is configured by addressing the register assigned to the desired output and writing the desired connection d ata into the f irst rank of latches in either m ap 0 or map 1. the connection data is equivalent to the binary co ded value of the input number. this process is repeated until each of the desired connections is programmed. in situations where multiple outpu ts are to be programmed to a single input, a b roadcast command is available. a broadcast command is issued by writing the binary value of the desired input to the xpt broadcast register (a ddress 0x82). the broad - cast is applied to the selected map as sele cted in the map table select register (a ddress 0x81). all output connections are updated simultaneously by passing the data from the first ran k of latches into the second rank by writing 0x 01 to the xpt update register (a ddress 0x80). this is a write - only register. t he update pin is edge sensitive. the switching time of the crosspoint array is measured from the v il level of the falling edge of the update signal to the 50% of the high - speed output signal transition. if the update strobe is unused, this pin should be pulled high the current state of the crosspoint connectivity is available by rea ding the xpt status registers (address 0xb0 to address 0xb7). register d escriptions for the map 0, m ap 1 and xpt status registe rs are provided in table 9 . a complete register map is provided in table 18. 07934-041 0 15 0 15 inputs outputs xpt core 0 15 0 15 inputs outputs register 0x90 t o register 0x97 xpt ma p 0 0 15 0 15 inputs outputs register 0x98 t o register 0x9f xpt ma p 1 0 1 map t able select register 0x81 xpt s ta tus read register 0xb0 t o register 0xb7 upd a te pin upd a te register 0x80 first rank registers second rank registers figure 41 . crosspoint connection map block diagram ADN4604 data sheet rev. a | page 18 of 40 table 9 . xpt control r egisters register name address bit bit name description default update 0x80 0 update updates xpt switch core (active high, write only) n/a map table select 0x81 0 map table select 0: map 0 is selected 0x00 1: map 1 is selected xpt broadcast 0x82 3:0 broadcast[3:0] all outputs connection assignment , write only n/a xpt map 0 control 0 0x90 7:4 out1[3:0] output 1 connection assignment 0xef 3:0 out0[3:0] output 0 connection assignment xpt map 0 control 1 0x91 7:4 out3[3:0] output 3 connection as signment 0xcd 3:0 out2[3:0] output 2 connection assignment xpt map 0 control 2 0x92 7:4 out5[3:0] output 5 connection assignment 0xab 3:0 out4[3:0] output 4 connection assignment xpt map 0 control 3 0x93 7:4 out7[3:0] output 7 connection assignme nt 0x89 3:0 out6[3:0] output 6 connection assignment xpt map 0 control 4 0x94 7:4 out9[3:0] output 9 connection assignment 0x67 3:0 out8[3:0] output 8 connection assignment xpt map 0 control 5 0x95 7:4 out11[3:0] output 11 connection assignment 0 x45 3:0 out10[3:0] output 10 connection assignment xpt map 0 control 6 0x96 7:4 out13[3:0] output 13 connection assignment 0x23 3:0 out12[3:0] output 12 connection assignment xpt map 0 control 7 0x97 7:4 out15[3:0] output 15 connection assignment 0x01 3:0 out14[3:0] output 14 connection assignment xpt map 1 control 0 0x98 7:4 out1[3:0] output 1 connection assignment 0x10 3:0 out0[3:0] output 0 connection assignment xpt map 1 control 1 0x99 7:4 out3[3:0] output 3 connection assignment 0x3 2 3:0 out2[3:0] output 2 connection assignment xpt map 1 control 2 0x9a 7:4 out5[3:0] output 5 connection assignment 0x54 3:0 out4[3:0] output 4 connection assignment xpt map 1 control 3 0x9b 7:4 out7[3:0] output 7 connection assignment 0x76 3 :0 out6[3:0] output 6 connection assignment xpt map 1 control 4 0x9c 7:4 out9[3:0] output 9 connection assignment 0x98 3:0 out8[3:0] output 8 connection assignment xpt map 1 control 5 0x9d 7:4 out11[3:0] output 11 connection assignment 0xba 3:0 o ut10[3:0] output 10 connection assignment xpt map 1 control 6 0x9e 7:4 out13[3:0] output 13 connection assignment 0xdc 3:0 out12[3:0] output 12 connection assignment xpt map 1 control 7 0x9f 7:4 out15[3:0] output 15 connection assignment 0xfe 3:0 out14[3:0] output 14 connection assignment xpt status 0 0xb0 7:4 out1[3:0] output 1 connection status , read only 0xef 3:0 out0[3:0] output 0 connection status , read only xpt status 1 0xb1 7:4 out3[3:0] output 3 connection status , read only 0xcd 3:0 out2[3:0] output 2 connection status , read only xpt status 2 0xb2 7:4 out5[3:0] output 5 connection status , read only 0xab 3:0 out4[3:0] output 4 connection status , read only xpt status 3 0xb3 7:4 out7[3:0] output 7 connection status , read only 0x89 3:0 out6[3:0] output 6 connection status , read only xpt status 4 0xb4 7:4 out9[3:0] output 9 connection status , read only 0x67 3:0 out8[3:0] output 8 connection status , read only xpt status 5 0xb5 7:4 out11[3:0] output 11 connection status , read only 0x45 3:0 out10[3:0] output 10 connection status , read only xpt status 6 0xb6 7:4 out13[3:0] output 13 connection status , read only 0x23 3:0 out12[3:0] output 12 connection status , read only xpt status 7 0xb7 7:4 out15[3:0] output 15 con nection status , read only 0x01 3:0 out14[3:0] output 14 connection status , read only data sheet ADN4604 rev. a | page 19 of 40 transmitters the ADN4604 transmitter outputs incorporate 50 termin- ation resistors, esd protection, and output current switches. each channel provides independent control of both the absolute output level and the preemphasis output level. note that the choice of output level affects the output common-mode level. on-chip termination esd v cc v ttox opx onx v ee v3 vc v2 vp v1 vn q1 it i dc + i pe q2 rp 50? rn 50? 07934-042 figure 42. simplified tx output circuit preemphasis transmission line attenuation can be equalized at the trans- mitter using preemphasis. the transmit equalizer setting can be chosen by matching the channel loss to the amount of boost provided by the preemphasis. basic settings in the basic mode of operation, predefined preemphasis settings are available through a lookup table. each table entry requires two bytes of memory. the amount of preemphasis provided is independent of the full-scale current output. transmitter preemphasis levels, as well as dc output levels, can be set through the serial control interface. the output level and amount of preemphasis can be independently programmed through advanced registers. by default, however, the total output amplitude and preemphasis setting space is reduced to a single table of basic settings that provides eight levels of output equalization to ease programming for typical fr4 channels. table 10 summarizes the absolute output level, preemphasis level, and high frequency boost for control setting. the full resolution of eight settings is available through the serial interface by writing to bits[2:0] (the tx pe[2:0] bits) of the basic tx control registers shown in table 11. a single setting is programmed to all outputs simultaneously by writing to the 0x18 broadcast address. the tx has four possible output enable states (disabled, standby, squelched, and enabled) controlled by the tx en[1:0] bits as shown in table 11. disabled is the lowest power-down state. when squelched, the output voltage at both p and n outputs will be the common-mode voltage as defined by the output current settings. in standby, the output level of both p and n outputs will be pulled up to the termination supply (v tton or v ttos ). the tx ctl select bit (bit 6) in the tx[15:0] basic control register determines whether the preemphasis and output current controls for the channel of interest are selected from the predefined lookup table or directly from the tx[15:0] drive control[1:0] registers (per channel). figure 43 is an illustration of the tx control circuit. setting the tx ctl select bit low (default setting) selects preemphasis control from the predefined, optimized lookup table (address 0x60 to address 0x6f). 07934-043 table entry 0 table entry 1 table entry 2 table entry 3 table entry 4 table entry 5 table entry 6 table entry 7 16 16 16 16 16 16 16 16 16 16 16 3 pe[2:0] tx ctl select ipx opx inx onx tx per output port lookup table basic settings per port output level advanced settings tx en[1:0] 2 figure 43. transmitter control block diagram in applications where the default preemphasis settings in the lookup table are not sufficient, the lookup table entries can be modified by programming the tx lookup table registers (0x60 to 0x6f) shown in table 12. in applications where the eight table entries are insufficient, each output can be programmed individually. table 10. preemphasis boost and overshoot vs. setting pe setting main tap current (ma) delayed tap current (ma) boost (db) overshoot (%) dc swing (mv p-p) 0 16 0 0.0 0 800 1 16 2 2.0 25 800 2 16 5 4.2 62.5 800 3 16 8 6.0 100 800 4 11 8 7.8 145 550 5 8 8 9.5 200 400 6 4 6 12.0 300 300 7 4 6 12.0 300 300 ADN4604 data sheet rev. a | page 20 of 40 table 11 displays the tx basic control register. the tx basic control register consists of one byte (8 bits) for each of the 16 output channels. each tx basic control register has the same functionality. the mapping of register address to output channel is shown in the first column. all outputs can be simultaneously programmed with a common output level, pre-emphasis and enable state using the tx broadcast register at address 0x18 as shown in table 11. note that this overwrites any data previously stored in addresses 0x20 to 0x2f. this register only affects the state of the tx basic control register and not the tx lookup table, tx advanced control, nor xpt control registers. table 11. tx basic control register address: channel default register name bit bit name description 0x18: broadcast 1 , 0x20: output 0, 0x21: output 1, 0x22: output 2, 0x23: output 3, 0x24: output 4, 0x25: output 5, 0x26: output 6, 0x27: output 7, 0x28: output 8, 0x29: output 9, 0x2a: output 10, 0x2b: output 11, 0x2c: output 12, 0x2d: output 13, 0x2e: output 14, 0x2f: output 15 0x00 tx basic control 6 tx ctl select 0: pe and output level control is derived from common lookup table 1: pe and output level control is derived from per port drive control registers 5:4 tx en[1:0] 00: tx disabled, lowest power state 01: tx standby. 10: tx squelched. 11: tx enabled 3 reserved reserved. set to 0. 2:0 pe[2:0] if tx ctl select = 0, see table 10 000: table entry 0 001: table entry 1 010: table entry 2 011: table entry 3 100: table entry 4 101: table entry 5 110: table entry 6 111: table entry 7 if tx ctl select = 1, pe[2:0] are ignored 1 the broadcast register, address 0x18, is write-only. table 12 displays the tx lookup table register. the tx lookup table register consists of two bytes (16 bits) for each of the ei ght possible table entries selected by the pe[2:0] field in table 11. the mapping of table entry to register address is shown in the first c olumn. by default, the tx lookup table register contains the preemphasis settings listed in table 10, however, these values can be change d for a flexible selection of output levels and preemphasis boosts. table 13 lists a variety of possible output level and preemphasis b oost settings and the corresponding tx drive 0 and tx drive 1 codes. table 12. tx lookup table registers address: channel default register name bit bit name description 0x60: table entry 0 0xff tx lookup table drive 0 7 drv en1 0: driver 1 disabled 1: driver 1 enabled 0x62: table entry 1 0xff 0x64: table entry 2 0xff 6:4 drv lv1[2:0] driver 1 current = decimal(drv lv1[2:0]) + 1 0x66: table entry 3 0xff 0x68: table entry 4 0xdc 3 drv en0 0: driver 0 disabled 1: driver 0 enabled 0x6a: table entry 5 0xbb 0x6c: table entry 6 0x99 2:0 drv lv0[2:0] driver 0 current = decimal(drv lv0[2:0]) + 1 0x6e: table entry 7 0x99 0x61: table entry 0 0x00 tx lookup table drive 1 7 drv end 0: driver d disabled 1: driver d enabled 0x63: table entry 1 0x99 0x65: table entry 2 0xcc 6:4 drv lvd[2:0] driver d current = decimal(drv lvd[2:0]) + 1 0x67: table entry 3 0xff 0x69: table entry 4 0xff 3 drv en2 0: driver 2 disabled 1: driver 2 enabled 0x6b: table entry 5 0xff 0x6d: table entry 6 0xdd 2:0 drv lv2[2:0] driver 2 current = decimal(drv lv2[2:0]) + 1 0x6f: table entry 7 0xdd data sheet ADN4604 rev. a | page 21 of 40 advanced settings in addition to the basic settings provided in the tx basic control registers, advanced settings are available in tx drive 0 control and tx drive 1 control registers (address 0x30 to address 0x4f). the advanced settings are useful in applications where each output requires an individually programmed preemphasis or output level setting beyond what is available in the lookup table in basic mode. to enable these advanced settings, set the tx ctl select bit in the tx basic control register to a logic high. next, program the tx drive 0 control and drive 1 control registers (address 0x30 to address 0x4f) to the desired output level and boost values. a subset of possible settings is provided in table 13. an expanded list of available settings is shown in table 19 in the applications information section. these advanced settings can also be used to modify the tx lookup table settings (address 0x60 to address 0x6f). the advanced settings register map is shown in table 15. the preemphasis boost equation follows. ) 1(log20]db[ 10 v vv dc sw dc sw pesw gain ? ? ? ? ??? (1) v tto v h-pe v sw-pe v l-pe v l-dc v sw-dc v h-dc v ocm t pe 07934-044 figure 44. signal level definitions table 13. tx preemphasis and output swing advanced settings single-ended output levels and pe boost register settings output current v sw-dc 1 (mv) v sw-pe 1 (mv) pe boost % pe (db) tx drive 0 tx drive 1 i tto 1 (ma) 200 200 0.00 0.00 0xbb 0x00 8 200 300 50.00 3.52 0xbb 0x99 12 200 350 75.00 4.86 0xbb 0xaa 14 200 400 100.00 6.02 0xbb 0xbb 16 200 450 125.00 7.04 0xbb 0xcc 18 200 500 150.00 7.96 0xbb 0xdd 20 200 600 200.00 9.54 0xbb 0xff 24 300 300 0.00 0.00 0xdd 0x00 12 300 400 33.33 2.50 0xdd 0x99 16 300 450 50.00 3.52 0xdd 0xaa 18 300 500 66.67 4.44 0xdd 0xbb 20 300 550 83.33 5.26 0xdd 0xcc 22 300 600 100.00 6.02 0xdd 0xdd 24 300 700 133.33 7.36 0xdd 0xff 28 400 400 0.00 0.00 0xff 0x00 16 400 500 25.00 1.94 0xff 0x99 20 400 550 37.50 2.77 0xff 0xaa 22 400 600 50.00 3.52 0xff 0xbb 24 400 650 62.50 4.22 0xff 0xcc 26 400 700 75.00 4. 86 0xff 0xdd 28 400 800 100.00 6.02 0xff 0xff 32 500 500 0.00 0.00 0xff 0x0b 20 600 600 0.00 0.00 0xff 0x0f 24 1 symbol definitions are shown in table 14. table 14. symbol definitions symbol formula definition i dc programmable output current that sets output level i pe programmable output curre nt for pe delayed tap i tto i dc + i pe total transmitter output current t pe preemphasis pulse width v dpp-dc 25 i dc 2 peak-to-peak differential voltage swing of non- preemphasized waveform v dpp-pe 25 i tto 2 peak-to-peak differential voltage swing of preemphasized waveform v sw-dc v dpp-dc /2 = v h-dc C v l-dc dc single-ended voltage swing v sw-pe v dpp-pe /2 = v h-pe C v l-pe preemphasized single-ended voltage swing ?v ocm_dc-coupled 25 i tto /2 output common-mode shif t, dc-coupled outputs ?v ocm_ac-coupled 50 i tto /2 output common-mode shif t, ac-coupled outputs v ocm v tto ? ?v ocm = ( v h-dc + v l-dc )/2 output common-mode voltage v h-dc v tto ? ?v ocm + v dpp-dc /2 dc single-ended output high voltage v l-dc v tto ? ?v ocm ? v dpp-dc /2 dc single-ended output low voltage v h-pe v tto ? ?v ocm + v dpp-pe /2 maximum single-ended output voltage v l-pe v tto ? ?v ocm ? v dpp-pe /2 minimum single-ended output voltage v tto output termination voltage ADN4604 data sheet rev. a | page 22 of 40 table 15 displays the tx advanced control r egister s. the tx advanced control r egister s consist of two bytes (16 bits) for each of the 16 output channels . the mapping of register address to output channel is shown in the first column. the tx advanced control register s provides ultimate flexibility of per port outp ut level and preemphasis boost. table 13 lists a variety of possible output level s and preemphasis boost settings and the corresponding tx drive 0 and tx drive 1 codes . table 15 . tx advanced control registers address: channel default register name bit bit name description 0x30: output 0, 0x32: outp ut 1, 0x34: output 2, 0x36: output 3, 0x38: output 4, 0x3a: output 5, 0x3c: output 6, 0x3e: output 7, 0x40: output 8, 0x42: output 9, 0x44: output 10, 0x46: output 11, 0x48: output 12, 0x4a: output 13, 0x4c: output 14, 0x4e: output 15 0xff tx drive 0 c ontrol 7 drv en1 0: driver 1 d isabled 1: driver 1 enabled 6:4 drv lv1[2:0] driver 1 current = decimal(drv lv1[2:0]) + 1 3 drv en0 0: driver 0 disabled 1: driver 0 enabled 2:0 drv lv0[2:0] driver 0 current = decimal(drv lv0 [2:0]) + 1 0x31: output 0, 0x33: output 1, 0x35: output 2, 0x37: output 3, 0x39: output 4, 0x3b: output 5, 0x3d: output 6, 0x3f: output 7, 0x41: output 8, 0x43: output 9, 0x45: output 10, 0x47: output 11, 0x49: output 12, 0x4b: output 13, 0x4d: output 14, 0x4f: output 15 0x00 tx drive 1 c ontrol 7 drv end 0: driver d disabled 1: driver d enabled 6:4 drv lvd[2:0] driver d current = decimal(drv lvd[2:0]) + 1 3 drv en2 0: driver 2 disabled 1: driver 2 enabled 2:0 drv lv2[2:0] driver 2 current = decimal(drv lv2[2:0]) + 1 data sheet ADN4604 rev. a | page 23 of 40 termination the inputs and outputs include integrated 50 termination resistors. for applications that require external termination resistors, the inter nal resistors can be disabled. for example, disabling the integrated 50 termination resistors allow s alternative termination values such as 75 as shown in figure 45. note that the integrated 50 termination resistors are optimal for hig h data rate digital signaling. disabling the terminations can reduce the overall performance. the termination control is separated by quadrants (north = outputs[15:8], south = outputs[7:0], east = inputs[15:8], and west = inputs[7:0]). table 16 shows the termination control register. a l ogic 0 enables the termination s for the respective quadrant. a l ogic 1 disables the t ermination s for the respective quadrant. the terminations are enabled by default. cm l 50? 50? 50? 50? 75? 75? v ee v tt ox 50? v tt ox v cc v ttix v ttix ADN4604 75? 75? 50? 50? 07934-045 rx figure 45 . 75 to 50 impedance translator. table 16 . termination control register address default register name bit bit name description 0xf0 0x00 termination c ontrol 3 txn_term output[15:8] (north) termination control 0: terminations e nabled 1: terminations d isabled 2 txs_term output[7:0] (south) termination control 0: terminations e nabled 1: terminations d isabled 1 rxe_term input[15:8 ] (east) termination control 0: terminations e nabled 1: terminations d isabled 0 rxw_term input[7: 0] (west) termination control 0: terminations e nabled 1: terminations d isabled ADN4604 data sheet rev. a | page 24 of 40 i 2 c serial control interface the ADN4604 register set is controlled through a 2-wire i 2 c interface. the ADN4604 acts only as an i 2 c slave device. therefore, the i 2 c bus in the system needs to include an i 2 c master to configure the ADN4604 and other i 2 c devices that may be on the bus. the ADN4604 i 2 c interface can be run in the standard (100 khz) and fast (400 khz) modes. the sda line only changes value when the scl pin is low with two exceptions. to indicate the beginning or continuation of a transfer, the sda pin is driven low while the scl pin is high; to indicate the end of a transfer, the sda line is driven high while the scl line is high. therefore, it is important to control the scl clock to toggle only when the sda line is stable unless indicating a start, repeated start, or stop condition. table 17. i 2 c device address assignment addr1 pin addr0 pin i 2 c device address 0 0 0x90 0 1 0x92 1 0 0x94 1 1 0x96 reset on initial power-up, or at any point in operation, the ADN4604 register set can be restored to the default values by pulling the reset pin to low according to the specification in table 2. during normal operation, however, the reset pin must be pulled up to dv cc . a software reset is available by writing the value 0x01 to the reset register at address 0x00. this register is write only. i 2 c data write to write data to the ADN4604 register set, a microcontroller, or any other i 2 c master, must send the appropriate control signals to the ADN4604 slave device. the steps to be followed are listed below; the signals are controlled by the i 2 c master, unless otherwise specified. a diagram of the procedure is shown in figure 46. 1. send a start condition (while holding the scl line high, pull the sda line low). 2. send the ADN4604 part address (seven bits) whose upper four bits are the static value b10010 and whose lower three bits are controlled by the input pins i2c_a[1:0]. this transfer should be msb first. 3. send the write indicator bit (0). 4. wait for the ADN4604 to acknowledge the request. 5. send the register address (eight bits) to which data is to be written. this transfer should be msb first. 6. wait for the ADN4604 to acknowledge the request. 7. send the data (eight bits) to be written to the register whose address was set in step 5. this transfer should be msb first. 8. wait for the ADN4604 to acknowledge the request. 9. do one or more of the following: a. send a stop condition (while holding the scl line high, pull the sda line high) and release control of the bus. b. send a repeated start condition (while holding the scl line high, pull the sda line low) and continue with step 2 of the write procedure to perform a write. c. send a repeated start condition (while holding the scl line high, pull the sda line low) and continue with step 2 of this procedure to perform a read from another address. d. send a repeated start condition (while holding the scl line high, pull the sda line low) and continue with step 8 of the read procedure (in the i2c data read section) to perform a read from the same address set in step 5. the ADN4604 write process is shown in figure 46. the scl signal is shown along with a general write operation and a specific example. in the example, data 0x92 is written to address 0x6d of an ADN4604 part with a part address of 0x4b. it is important to note that the sda line only changes when the scl line is low, except for the case of sending a start, stop, or repeated start condition, step 1 and step 9 in this case. start r/w ack ack ack stop data addr [1:0] b10010 register addr scl sda sda example 1 2 2 3 4 5 6 7 8 9a 07934-046 figure 46. i 2 c write diagram data sheet ADN4604 rev. a | page 25 of 40 i 2 c data read to read data from the ADN4604 register set, a microcontroller, or any other i 2 c master must send the appropriate control signals to the ADN4604 slave device. the steps are listed below; the signals are controlled by the i 2 c master, unless otherwise specified. a diagram of the procedure is shown in figure 47. 1. send a start condition (while holding the scl line high, pull the sda line low). 2. send the ADN4604 part address (seven bits) whose upper five bits are the static value b10010 and whose lower two bits are controlled by the input pins addr1 and addr0. this transfer should be msb first. 3. send the write indicator bit (0). 4. wait for the ADN4604 to acknowledge the request. 5. send the register address (eight bits) from which data is to be read. this transfer should be msb first. the register address is kept in memory in the ADN4604 until the part is reset or the register address is written over with the same procedure (step 1 to step 6). 6. wait for the ADN4604 to acknowledge the request. 7. send a repeated start condition (while holding the scl line high, pull the sda line low). 8. send the ADN4604 part address (seven bits) whose upper five bits are the static value b10010 and whose lower two bits are controlled by the input pins addr1 and addr0. this transfer should be msb first. 9. send the read indicator bit (1). 10. wait for the ADN4604 to acknowledge the request. 11. the ADN4604 then serially transfers the data (eight bits) held in the register indicated by the address set in step 5. 12. acknowledge the data. 13. do one or more of the following: a. send a stop condition (while holding the scl line high pull the sda line high) and release control of the bus. b. send a repeated start condition (while holding the scl line high, pull the sda line low) and continue with step 2 of the write procedure (see the i 2 c data write section) to perform a write. c. send a repeated start condition (while holding the scl line high, pull the sda line low) and continue with step 2 of this procedure to perform a read from another address. d. send a repeated start condition (while holding the scl line high, pull the sda line low) and continue with step 8 of this procedure to perform a read from the same address. the ADN4604 read process is shown in figure 47. the scl signal is shown along with a general read operation and a specific example. in the example, data 0x49 is read from address 0x6d of an ADN4604 part with a part address of 0x4b. the part address is seven bits wide and is composed of the ADN4604 static upper five bits (b10010) and the pin program- mable lower two bits (addr1 and addr0). in this example, the addr1 and addr0 bits are set to b01. in figure 47, the corresponding step number is visible in the circle under the waveform. the scl line is driven by the i 2 c master and never by the ADN4604 slave. as for the sda line, the data in the shaded polygons is driven by the ADN4604, whereas the data in the nonshaded polygons is driven by the i 2 c master. the end phase case shown is that of 13a. note that the sda line only changes when the scl line is low, except for the case of sending a start, stop, or repeated start condition, as in step 1, step 7, and step 13. in figure 47, a is the same as ack in figure 46. equally, sr represents a repeated start where the sda line is brought high before scl is raised. sda is then dropped while scl is still high. scl sda sda example 1 2 2 3 4 5 6 7 8 8 9 10 11 12 13a b10010 a a sr data a stop register addr start addr [1:0] addr [1:0] b10010 r/ w a r/ w 0 7934-047 figure 47. i 2 c read diagram ADN4604 data sheet rev. a | page 26 of 40 spi serial control interface the spi serial interface of the ADN4604 consists of four wires: cs , sck, sdi, and sdo. cs is used to select the device when more than one device is connected to the serial clock and data lines. cs is also used to distinguish between read and write commands (see figure 48). sck is used to clock data in and out of the part. data can either contain eight bits of register address or data. the sdi line is used to write to the registers, and the sdo line is used to read data back from the registers. data on sdi is clocked on the rising edge of sck. data on sdo changes on the falling edge of sck. the recommended pull-up resistor value is between 500 and 1 k. strong pull-ups are needed when serial clock speeds that are close to the maximum limit are used or when the spi interface lines are experiencing large capacitive loading. larger resistor values can be used for pull-up resistors when the serial clock speed is reduced. the part operates in slave mode and requires an externally applied serial clock to the sclk input. the serial interface is designed to allow the part to be interfaced to systems that provide a serial clock that is synchronized to the serial data. write operation figure 48 shows the diagram for a write operation to the ADN4604. data is clocked into the registers on the rising edge of sck. when the cs line is high, the sdi and sdo lines are in three-state mode. only when the cs goes from high to low does the part accept any data on the sdi line. to allow continuous writes, the address pointer register auto-increments by one without having to load the address pointer register each time. subsequent data bytes are written into sequential registers. note that not all registers in the 256-byte address space exist and not all registers are writable. zeroes should be entered for nonexisting address fields when implementing a continuous write operation. address 0xd0 to address 0xef are reserved and should not be overwritten. a continuous write sequence is shown in figure 49. read operation figure 48 shows the diagram for a write operation to the ADN4604. to read back from a register, first write to the address pointer register with the desired starting address. a read command is distinguished from a write command by the occurrence of cs going high after the address pointer is written. subsequent clock cycles with cs asserted low stream data starting from the desired register address onto sdo, msb first. sdo changes on the falling edge of sck. multiple data reads are possible in spi interface mode as the address pointer register is auto-incremented. a continuous read sequence is shown in figure 50. sdi address xxxxxxxx sd o data cs write operation hi-z hi-z read operation sdi address data sd o cs 07934-048 figure 48. spicorrect use of cs during spi communications data sheet ADN4604 rev. a | page 27 of 40 address data byte 0 data byte 1 data byte n cs sck sdi sdo hi-z 07934-049 figure 49. spi continuous write sequence address xxxxxxxx xxxxxxxx xxxxxxxx cs sck sdi sdo hi-z data byte 0 data byte 1 data byte n 07934-050 figure 50. spi continuous read sequence ADN4604 data sheet rev. a | page 28 of 40 register map registers repeated per port or per tab le entry are grouped together. register address mapping is shown in the first column. table 18 . register map address : channel default register name bit bit name description 0x00 n/a reset 0 r eset software reset. write only. 0x10 0xff rx eq control 0 7 eq[7] equalizer boost control for input 7 0: 0 db 1: 12 db 6 eq[6] equalize r boost control for i nput 6 5 eq [ 5] equalizer boost control for i nput 5 4 eq [ 4] equalizer boost control for i nput 4 3 eq [ 3] equalizer boost control for i nput 3 2 eq [ 2] equalizer boost control for i nput 2 1 eq [ 1] equalizer boost control for input 1 0 eq[0 ] equalizer boost control for i nput 0 0x11 0xff rx eq control 1 15 eq [ 15] equalizer boost control for i nput 15 0: 0 db 1: 12 db 14 eq [ 14] equalizer boost control for i nput 14 13 eq [ 13] equalizer boost control for i nput 13 12 eq [ 12] equalizer boost control for i nput 12 11 eq [ 11] equalizer boost control for i nput 11 10 eq [ 10] equalizer boost control for input 10 9 eq [ 9] equalizer boost control for i nput 9 8 eq [ 8] equalizer boost control for i nput 8 0x12 0x00 rx control 0 7 sign[7] signal path polarity inversion for i nput 7 0: noninverting 1: inverting 6 sign[6] signal path polarity inversion for i nput 6 5 sign[ 5] signal path polarity inversion for input 5 4 sign[ 4] signal p ath polarity inversion for input 4 3 sign[ 3] signal path polarity inversion for input 3 2 sign[ 2] signal path polarity inversion for i nput 2 1 sign[ 1] signal path polarity inversion for i nput 1 0 sign[ 0] signal path polarity inversion for i nput 0 0x13 0x00 rx control 1 15 sign[ 15] signal path polarity inversion for i nput 15 0: noninverting 1: inverting 14 sign[ 14] signal path polarity inversion for i nput 14 13 sign[ 13] signal path polarity inversion for i nput 13 12 s ign[ 12] signal path polarity inversion for in put 12 11 sign[ 11] signal path polarity inversion for i nput 11 10 sign[ 10] signal path polarity inversion for i nput 10 9 sign[ 9] signal path polarity inversion for i nput 9 8 sign[ 8] signal path p olarity inversion for i nput 8 data sheet ADN4604 rev. a | page 29 of 40 address : channel default register name bit bit name description 0x18: broadcast 1 , 0x20: output 0 , 0x21: output 1 , 0x22: output 2 , 0x23: output 3 , 0x24: output 4 , 0x25: output 5 , 0x26: output 6 , 0x27: output 7 , 0x28: output 8 , 0x29: output 9 , 0x2a: output 10 , 0x2b: output 11 , 0x2c: output 12 , 0x2d: output 13 , 0x2e: output 14 , 0x2f: output 15 0x00 tx basic c ontrol 6 tx ctl select 0: pe and output level control is derived from common look up table 1: pe and output level control is derived from per port drive control registers 5:4 tx en[1:0] 00: tx d isabled, lowest power state 01: tx s tandby 10: tx s quelched 11: tx e nabled 3 reserved reserved. s et to 0 . 2:0 pe[2:0] if tx ctl select = 0, see table 10 selected table entr y = decimal(pe[2:0]) if tx ctl select = 1, pe[2:0] are ignored 0x30: output 0 , 0x32: output 1 , 0x34: output 2 , 0x36: output 3 , 0x38: output 4 , 0x3a: output 5 , 0x3c: output 6 , 0x3e: output 7 , 0x40: output 8 , 0x42: output 9 , 0x44: output 10 , 0x46: output 11 , 0x48: output 12 , 0x4a: output 13 , 0x4c: output 14 , 0x4e: output 15 0xff tx drive 0 c ontrol 7 drv en1 0: driver 1 d isabled 1: driver 1 e nabled 6:4 drv lv1[2:0] driver 1 c urrent = decimal(drv lv1[2:0]) + 1 3 drv en0 0: driver 0 d isabled 1: driver 0 enabled 2:0 drv lv0[2:0] driver 0 c urrent = decimal(drv lv0[2:0]) + 1 0x31: output 0 , 0x33: output 1 , 0x35: output 2 , 0x37: output 3 , 0x39: output 4 , 0x3b: output 5 , 0x3d: output 6 , 0x3f: output 7 , 0x41: output 8 , 0x43: outp ut 9 , 0x45: output 10 , 0x47: output 11 , 0x49: output 12 , 0x4b: output 13 , 0x4d: output 14 , 0x4f: output 15 0x00 tx drive 1 c ontrol 7 drv end 0: driver d d isabled 1: driver d enabled 6:4 drv lvd[2:0] driver d c urrent = decimal(drv lvd[2:0]) + 1 3 drv en2 0: driver 2 d isabled 1: driver 2 e nabled 2:0 drv lv2[2:0] driver 2 c urrent = decimal(drv lv2[2:0]) + 1 0x60: table entry 0 0xff tx l ookup table 0 7 drv en1 0: driver 1 d isabled 1: driver 1 e nabled 0x62: table entry 1 0xff 0x64: tabl e entry 2 0xff 6:4 drv lv1[2:0] driver 1 c urrent = decimal(drv lv1[2:0]) + 1 0x66: table entry 3 0xff 0x68: table entry 4 0xdc 3 drv en0 0: driver 0 d isabled 1: driver 0 e nabled 0x6a: table entry 5 0xbb 0x6c: table entry 6 0x99 2:0 drv lv0[2 :0] driver 0 c urrent = decimal(drv lv0[2:0]) + 1 0x6e: table entry 7 0x99 ADN4604 data sheet rev. a | page 30 of 40 address : channel default register name bit bit name description 0x61: table entry 0 0x00 tx l ookup table 1 7 drv end 0: driver d d isabled 1: driver d e nabled 0x63: table entry 1 0x99 0x65: table entry 2 0xcc 6:4 drv lvd[2:0] driver d c urrent = decimal(drv lvd[2:0]) + 1 0x67: table entry 3 0xff 0x69: table entry 4 0xff 3 drv en2 0: driver 2 d isabled 1: driver 2 e nabled 0x6b: table entry 5 0xff 0x6d: table entry 6 0xdd 2:0 drv lv2[2:0] driver 2 c urrent = decimal(drv lv2[2 :0]) + 1 0x6f: table entry 7 0xdd 0x80 write only update 0 update updates xpt switch core ( a ctive high, write only) 0x81 0x00 map table select 0 map table select 0: map 0 is selected 1: map 1 is selected 0x82 w rite only xpt b roadcast 3:0 broadcas t[3:0] all outputs connection assignment 0x90 0xef xpt map 0 control 0 7:4 out1[3:0] output 1 connection assignment 3:0 out0[3:0] output 0 connection assignment 0x91 0xcd xpt map 0 control 1 7:4 out3[3:0] output 3 connection assignment 3:0 out2[3 :0] output 2 connection assignment 0x92 0xab xpt map 0 control 2 7:4 out5[3:0] output 5 connection assignment 3:0 out4[3:0] output 4 connection assignment 0x93 0x89 xpt map 0 control 3 7:4 out7[3:0] output 7 connection assignment 3:0 out6[3:0] ou tput 6 connection assignment 0x94 0x67 xpt map 0 control 4 7:4 out9[3:0] output 9 connection assignment 3:0 out8[3:0] output 8 connection assignment 0x95 0x45 xpt map 0 control 5 7:4 out11[3:0] output 11 connection assignment 3:0 out10[3:0] outpu t 10 connection assignment 0x96 0x23 xpt map 0 control 6 7:4 out13[3:0] output 13 connection assignment 3:0 out12[3:0] output 12 connection assignment 0x97 0x01 xpt map 0 control 7 7:4 out15[3:0] output 15 connection assignment 3:0 out14[3:0] out put 14 connection assignment 0x98 0x10 xpt map 1 control 0 7:4 out1[3:0] output 1 connection assignment 3:0 out0[3:0] output 0 connection assignment 0x99 0x32 xpt map 1 control 1 7:4 out3[3:0] output 3 connection assignment 3:0 out2[3:0] output 2 connection assignment 0x9a 0x54 xpt map 1 control 2 7:4 out5[3:0] output 5 connection assignment 3:0 out4[3:0] output 4 connection assignment 0x9b 0x76 xpt map 1 control 3 7:4 out7[3:0] output 7 connection assignment 3:0 out6[3:0] output 6 conne ction assignment 0x9c 0x98 xpt map 1 control 4 7:4 out9[3:0] output 9 connection assignment 3:0 out8[3:0] output 8 connection assignment 0x9d 0xba xpt map 1 control 5 7:4 out11[3:0] output 11 connection assignment 3:0 out10[3:0] output 10 connect ion assignment 0x9e 0xdc xpt map 1 control 6 7:4 out13[3:0] output 13 connection assignment 3:0 out12[3:0] output 12 connection assignment 0x9f 0xfe xpt map 1 control 7 7:4 out15[3:0] output 15 connection assignment 3:0 out14[3:0] output 14 conne ction assignment data sheet ADN4604 rev. a | page 31 of 40 address : channel default register name bit bit name description 0xb0 0xef xpt status 0 7:4 out1[3:0] output 1 connection status 3:0 out0[3:0] output 0 connection status 0xb1 0xcd xpt status 1 7:4 out3[3:0] output 3 connection status 3:0 out2[3:0] output 2 connection status 0xb2 0xab xpt stat us 2 7:4 out5[3:0] output 5 connection status 3:0 out4[3:0] output 4 connection status 0xb3 0x89 xpt status 3 7:4 out7[3:0] output 7 connection status 3:0 out6[3:0] output 6 connection status 0xb4 0x67 xpt status 4 7:4 out9[3:0] output 9 connecti on status 3:0 out8[3:0] output 8 connection status 0xb5 0x45 xpt status 5 7:4 out11[3:0] output 11 connection status 3:0 out10[3:0] output 10 connection status 0xb6 0x23 xpt status 6 7:4 out13[3:0] output 13 connection status 3:0 out12[3:0] o utput 12 connection status 0xb7 0x01 xpt status 7 7:4 out15[3:0] output 15 connection status 3:0 out14[3:0] output 14 connection status 0xf0 0x00 termination c ontrol 3 txn_term output[15:8] (north) termination control 0: terminations e nabled 1: termi nations d isabled 2 txs_term output[7:0] (south) termination control 1 rxe_term input[15:8 ] (east) termination control 0 rxw_term input[7:0] (west) termination control 0xfe revision 7:0 rev[7:0] read - only 0xff 0x04 device id 7:0 id[7:0] read - only 1 broadcast register, address 0x18, is write - only. ADN4604 data sheet rev. a | page 32 of 40 applications informa tion the ADN4604 is an asynchronous and protocol agnostic digital switch and , therefore , is applicable to a wide range of applica - tions including network routin g and digital video switching. the ADN4604 supports the data rate s and signaling le vels of hdmi ? , dvi ? , displayport and sd - , hd - , and 3g - sdi digital video. the ADN4604 can be us ed to create matrix switches. a n example block diagram of a 16 16 matrix switch is shown in figure 51. since hdmi, d vi , and displayport are quad lane protocols, four ADN4604s are used to create a full 16 16 matrix switch. smaller arrays , such as 4 4 and 8 8 , require one and two ADN4604 devices, respectively. proper high speed pcb design techniques should be used t o maintain the signal integrity of the high data rate signals. it is important to minimize the lane - to - lane skew and crosstalk in these applications. ADN4604 in 0 in 1 in 15 out 0 out 1 out 15 ADN4604 in 0 in 1 in 15 out 0 out 1 out 15 ADN4604 in 0 in 1 in 15 out 0 out 1 out 15 ADN4604 in 0 in 1 in 15 out 0 out 1 out 15 source 1 source 2 source 16 source 3 source 4 source 5 source 6 source 7 source 8 source 9 source 10 source 1 1 source 12 source 13 source 14 source 15 displ a y 1 displ a y 2 displ a y 16 displ a y 3 displ a y 4 displ a y 5 displ a y 6 displ a y 7 displ a y 8 displ a y 9 displ a y 10 displ a y 1 1 displ a y 12 displ a y 13 displ a y 14 displ a y 15 07934-051 figure 51 . ADN4604 digital video (dvi, hdmi, displayport) matrix switch bloc k diagram data sheet ADN4604 rev. a | page 33 of 40 o/e o/e e/o e/o cdr cdr o/e e/o cdr ADN4604 16 16 crosspoint switch in 1 in 2 in 15 out 1 out 2 out 15 07934-052 figure 52 . ADN4604 networking switch application block diagram pe eq loss y channe l 8 lane uplink pa th 8 lane downlink pa th loss y channe l asic 2 eq pe asic 1 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 07934-053 figure 53 . multi - l ane signal conditioning application diagram ADN4604 data sheet rev. a | page 34 of 40 supply sequencing ideally, all power supplies should be brou ght up to the appropri - ate levels simultaneously (power supply requirements are set by the supply limits in table 1 and the absolute maximum ratings listed in table 4 ). if the power supplies to the adn460 4 are brought up separately, the supply power - up sequence is as follows: dv cc powered first, followed by v cc , and , last the termination supplies ( v tti e , v tti w , v tton , and v tto s ) . the power - down sequence is reversed with termination supplies being powered o ff first. the termination supplies contain esd protection diodes to the v cc power domain . to avoid a sustained high current condition in these devices (i sustained < 100 ma), the v tti and v tto supplies should be powered on after v cc and should be powered of f before v cc . if the system power supplies have a high impedance in the powered off state, then supply sequencing is not required provided the following limits are observed: ? peak current from v tti x or v tto x to v cc < 200 ma ? sustained current from v tti x or v tto x to v cc < 100 ma power dissipation the power dissipation of the ADN4604 depends on the supply voltages, i/o coupling t ype, and device configuration. the input termination resistors dissipate power depending on the differential input swing and common - m ode volta ge. when ac - coupled, the common - mode voltage is equal to the termination s upply voltage (v ttie or v ttiw ). while the current drawn from the input termination supply is effectively zero, there is still power and heat dissipated in the termination re sistors as a result of the differential signal swing. the core supply current and output termination current are strongly dependent on device configuration, such as the number of channels enabled, output level setting, and output preemphasis setting. in high ambient temperature operating conditions, it is impor - tant to avoid exceeding the maximum junc tion temperature of the device. limiting the total power dissipation can be achieved by the following: ? r educing the output swing ? r educing the preemphasis lev el ? d ecreasing the supply voltages within the allowable ranges defined in table 1 ? d isabling unused channels alternatively, the therm al resistance can be reduced by ? a dding an external heat - sink ? increasing the air flo w refer to the printed circuit board (pcb) layout guidelines section for recommendations for proper thermal stencil layout and fabrication. output compliance in low voltage applications, users must pay careful attention to both t he differential and common - mode signal level. the choice of output voltage swing, preemphasis setting, supply voltages (v cc and v tto ), and output coupling (ac or dc) affect peak and settled single - ended voltage swings and the common - mode shift measured acr oss the output termination resistors. these choices also affect output current and, consequently, power consumption. table 19 sh ows the change in output common mode (v ocm = v cc ? v ocm ) with output leve l and preemphasis setting. s ingle - ended output levels are calculated for v tto supplies of 3.3 v and 2.5 v to illustrate practical challenges of reducing the supply voltage. the minimum v l (min v l ) cannot be below t he absolute minimum level specified in table 1 . the combinations of output level, preemphasis, supply voltage , and output coupling for which the minimum v l specifica tion is violated are listed as n/a in ta ble 1 . since the absolute minimum output voltage specified in tabl e 1 is relative to v cc , decreasing v cc is required to maintain the output levels within the specified limits when lower output term ination voltages are required. v tto voltages as low as 1.8 v are allowable for output swings less than or equal to 400 mv (single - ended). figure 54 illustrates an application wh ere the ADN4604 is used as a dc - coupled level translator to interface a 3.3 v cml d riv er to an asic with 1.8 v i/os. the diode in series with v cc reduces the voltage at v cc for improved output compliance. cm l v ee v tt ox 1.8v 1.8v 3.3v 3.3v v cc v ttix ADN4604 cm l 3.3v z 0 z 0 z 0 z 0 07934-054 asic rx figure 54 . dc - coupled level translator application circuit data sheet ADN4604 rev. a | page 35 of 40 table 19. output volt age range and output common - mode shift vs. output level and pe setting single - ended output levels and pe boos t register settings output current ac - coupled outputs dc - coupled outputs v cc = v tto = 3.3 v v cc = 2.7 v v tto = 2.5 v v cc = v tto = 3.3 v v c c = 2.7 v v tto = 2.5 v v sw - dc 1 (mv) v sw - pe 1 (mv) pe boost % pe (db) tx drive 0 tx drive 1 i tto 1 (ma) ?v ocm 1 (mv) v h - pe 1 (v) v l - pe 1 (v) v h - pe 1 (v) v l - pe 1 (v) ?v ocm 1 (mv) v h - dc 1 (v) v l - dc 1 (v) v h - pe 1 (v) v l - pe 1 (v) 100 100 0.00 0.00 0x99 0x00 4 100 3.25 3.15 2.45 2.35 50 3.3 3.2 2.5 2.4 100 150 50.00 3.52 0x99 0x88 6 150 3.225 3.075 2.425 2.275 75 3.3 3.15 2.5 2.35 100 200 100.00 6.02 0x99 0x99 8 200 3.2 3 2.4 2.2 100 3.3 3.1 2.5 2.3 100 250 150.00 7.96 0x99 0xaa 10 250 3.175 2.925 2.375 2.125 125 3.3 3.05 2.5 2.25 100 300 200.00 9.54 0x99 0xbb 12 300 3.15 2.85 2.35 2.05 150 3.3 3 2.5 2.2 100 350 250.00 10.88 0x99 0xcc 14 350 3.125 2.775 2.325 1.975 175 3.3 2.95 2.5 2.15 100 400 300.00 12.04 0x99 0xdd 16 400 3.1 2.7 2.3 1.9 200 3.3 2.9 2.5 2.1 100 450 350.00 13.06 0x99 0xee 18 450 3.075 2.625 2.275 1.825 225 3.3 2.85 2.5 2.05 100 500 400.00 13.98 0x99 0xff 20 500 3.05 2.55 2.25 1.75 250 3.3 2.8 2.5 2 200 200 0.00 0.00 0xbb 0x00 8 200 3.2 3 2.4 2.2 100 3.3 3.1 2.5 2.3 200 250 25.00 1.94 0xbb 0x88 10 250 3.175 2.925 2.375 2.125 125 3.3 3.05 2.5 2.25 200 300 50.00 3.52 0xbb 0x99 12 300 3.15 2.85 2.35 2.05 150 3.3 3 2.5 2.2 200 350 75.00 4.86 0xbb 0xaa 14 350 3.125 2.775 2.325 1.975 175 3.3 2.95 2.5 2.15 200 400 100.00 6.02 0xbb 0xbb 16 400 3.1 2.7 2.3 1.9 200 3.3 2.9 2.5 2.1 200 450 125.00 7.04 0xbb 0xcc 18 450 3.075 2.625 2.275 1.825 225 3.3 2.85 2.5 2.05 200 500 150.00 7.96 0xbb 0xdd 20 500 3.05 2.55 2.25 1.75 250 3.3 2.8 2.5 2 200 550 175.00 8.79 0xbb 0xee 22 550 3.025 2.475 2.225 1.675 275 3.3 2.75 2.5 1.95 200 600 200.00 9.54 0xbb 0xff 24 600 3 2.4 2.2 1.6 300 3.3 2.7 2.5 1.9 300 300 0.00 0.00 0xdd 0x00 12 300 3.15 2.85 2.35 2.05 150 3.3 3 2.5 2.2 300 350 16.67 1.34 0xdd 0x88 14 350 3.125 2.775 2.325 1.975 175 3.3 2.95 2.5 2.15 300 400 33.33 2.50 0xdd 0x99 16 400 3.1 2.7 2.3 1.9 200 3.3 2.9 2.5 2.1 300 450 50.00 3.52 0xdd 0xaa 18 450 3.075 2.625 2.275 1.825 225 3.3 2.85 2.5 2.05 300 500 66.67 4.44 0xdd 0xbb 20 500 3.05 2.55 2.25 1.75 250 3.3 2.8 2.5 2 300 550 83.33 5.26 0xdd 0xcc 22 550 3.025 2.475 2.225 1.675 275 3.3 2.75 2.5 1.95 300 600 100.00 6.02 0xdd 0xdd 24 600 3 2.4 2.2 1.6 300 3.3 2.7 2.5 1.9 300 650 116.67 6.72 0xdd 0 xee 26 650 2.975 2.325 2.175 1.525 325 3.3 2.65 2.5 1.85 300 700 133.33 7.36 0xdd 0xff 28 700 2.95 2.25 2.15 1.45 350 3.3 2.6 2.5 1.8 400 400 0.00 0.00 0xff 0x00 16 400 3.1 2.7 2.3 1.9 200 3.3 2.9 2.5 2.1 400 450 12.50 1.02 0xff 0x88 18 450 3.075 2.625 2.275 1.825 225 3.3 2.85 2.5 2.05 400 500 25.00 1.94 0xff 0x99 20 500 3.05 2.55 2.25 1.75 250 3.3 2.8 2.5 2 400 550 37.50 2.77 0xff 0xaa 22 550 3.025 2.475 2.225 1.675 275 3.3 2.75 2.5 1.95 400 600 50.00 3.52 0xff 0xbb 24 600 3 2.4 2.2 1.6 300 3.3 2.7 2 .5 1.9 400 650 62.50 4.22 0xff 0xcc 26 650 2.975 2.325 2.175 1.525 325 3.3 2.65 2.5 1.85 400 700 75.00 4.86 0xff 0xdd 28 700 2.95 2.25 2.15 1.45 350 3.3 2.6 2.5 1.8 400 750 87.50 5.46 0xff 0xee 30 750 2.925 2.175 n/a 2 n/a 2 375 3.3 2.55 2.5 1.75 400 800 100.00 6.02 0xff 0xff 32 800 2.9 2.1 n/a 2 n/a 2 400 3.3 2.5 2.5 1.7 450 450 0.00 0.00 0xff 0x09 18 450 3.075 2.625 2. 275 1.825 225 3.3 2.85 2.5 2.05 450 650 44.44 3.19 0xff 0xbd 26 650 2.975 2.325 2.175 1.525 325 3.3 2.65 2.5 1.85 500 500 0.00 0.00 0xff 0x0b 20 500 3.05 2.55 n/a 2 n/a 2 250 3.3 2.8 2.5 2 500 700 40.00 2.92 0xff 0xbf 28 700 2.95 2.25 2.15 1.45 350 3.3 2.6 2.5 1.8 550 550 0.00 0.00 0xff 0x0d 22 550 3.025 2.475 2.225 1.675 275 3.3 2.75 2.5 1.95 550 650 18.18 1.45 0xff 0x9f 26 650 2.975 2.325 2.175 1.525 325 3.3 2.6 5 2.5 1.85 600 600 0.00 0.00 0xff 0x0f 24 600 3 2.4 n/a 2 n/a 2 300 3.3 2.7 2.5 1.9 1 symbol definitions are shown in table 14. 2 this setting is not allowed when ac - coupled with v cc = 2.7 v a nd v tton = 2.5 v or v ttos = 2.5 v. ADN4604 data sheet rev. a | page 36 of 40 printed circuit board (pcb) layout guidelines the high speed differential inputs and outputs should be routed with 100 controlled impedance differential transmission lines. the transmission lines, either microstrip or stripline, should be referenced to a solid low impedance reference plane. an example of a pcb cross-section is shown in figure 55. the trace width (w), differential spacing (s), height above reference plane (h), and dielectric constant of the pcb material determine the characteristic impedance. adjacent channels should be kept apart by a distance greater than 3 w to minimize crosstalk. pcb dielectric signal (microstrip) soldermask pcb dielectric pcb dielectric pcb dielectric reference plane reference plane signal (stripline) wsw h wsw 0 7934-055 figure 55. example of a pcb cross-section thermal paddle design the tqfp is designed with an exposed thermal paddle to conduct heat away from the package and into the pcb. by incorporating thermal vias into the pcb thermal paddle, heat is dissipated more effectively into the inner metal layers of the pcb. to ensure device performance at elevated temperatures, it is important to have a sufficient number of thermal vias incorporated into the design. an insufficient number of thermal vias results in a ja value larger than specified in table 1. it is recommended that a via array of 4 4 or 5 5 with a diameter of 0.3 mm to 0.33 mm be used to set a pitch between 1.0 mm and 1.2 mm. a representative of these arrays is shown in figure 56. thermal via thermal paddle 07934-056 figure 56. pcb thermal paddle and via stencil design for the thermal paddle to effectively remove heat from the package and to enhance electrical performance, the thermal paddle must be soldered (bonded) to the pcb thermal paddle, preferably with minimum voids. however, eliminating voids may not be possible because of the presence of thermal vias and the large size of the thermal paddle for larger size packages. also, outgassing during the reflow process may cause defects (splatter, solder balling) if the solder paste coverage is too big. it is recommended that smaller multiple openings in the stencil be used instead of one big opening for printing solder paste on the thermal paddle region. this typically results in 50% to 80% solder paste coverage. figure 57 shows how to achieve these levels of coverage. voids within solder joints under the exposed paddle can have an adverse affect on high speed and rf applications, as well as on thermal performance. because the package incorporates a large center paddle, controlling solder voiding within this region can be difficult. voids within this ground plane can increase the current path of the circuit. the maximum size for a void should be less than via pitch within the plane. this assures that any one via is not rendered ineffectual when any void increases the current path beyond the distance to the next available via. 1.35mm 1.35mm squares at 1.65mm pitch coverage: 68% 07934-057 figure 57. typical thermal paddle stencil design data sheet ADN4604 rev. a | page 37 of 40 large voids in the thermal paddle area should be avoided. to control voids in the thermal paddle area, solder masking may be required for thermal vias to prevent solder wicking inside the via during reflow, thus displacing the solder away from the interface between the package thermal paddle and thermal paddle land on the pcb. there are several methods employed for this purpose, such as via tenting (top or bottom side), using dry film solder mask; via plugging with liquid photo-imagible (lpi) solder mask from the bottom side; or via encroaching. these options are depicted in figure 58. in case of via tenting, the solder mask diameter should be 100 microns larger than the via diameter. (a) (b) (d) (c) via solder mask coppe r plating 07934-058 figure 58. solder mask options for thermal vias: (a) via tenting from the top; (b) via tenting from the bottom; (c) via plugging, bottom; and (d) via encroaching, bottom ADN4604 data sheet rev. a | page 38 of 40 outline dimensions compliant to jedec standards ms-026-aed-hd 021809-a 1 25 26 50 76 100 75 51 14.00 bsc sq 16.00 bsc sq 0.27 0.22 0.17 0.50 bsc 1.05 1.00 0.95 0.15 0.05 0.75 0.60 0.45 seating plane 1.20 max 1 25 26 50 76 100 75 51 6.50 nom 7 3.5 0 coplanarity 0.08 0.20 0.09 top view (pins down) bottom view (pins up) conductive heat sink pin 1 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 59. 100-lead thin quad flat package, exposed pad [tqfp_ep] (sv-100-1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ordering quantity ADN4604asvz ?40c to +85c 100-lead thin quad flat package [tqfp_ep] sv-100-1 ADN4604asvz-rl ?40c to +85c 100-lead thin quad flat package [tqfp_ep], 13 tape & reel sv-100-1 1000 ADN4604-evalz evaluation board 1 z = rohs compliant part . data sheet ADN4604 rev. a | page 39 of 40 notes ADN4604 data sheet rev. a | page 40 of 40 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2009C2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07934-0-3/13(a) |
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